Bulldog : a compiler for VLIW architectures
Lx: a technology platform for customizable VLIW embedded processing
The Superblock: An Effective Technique for VLIW and Superscalar Compilation
The superblock: An effective technique for VLIW and superscalar compilation
Software pipelining: an effective scheduling technique for VLIW machines
Software pipelining: an effective scheduling technique for VLIW machines
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Lam, M.: Software pipelining: An effective scheduling technique for VLIW machines. SIGPLAN Not. 23(7), 318-328